According to the examination on the technologies for a delay locked loop circuit by the inventor of the present invention, for example, the following technologies are known.
In general, a delay locked loop (DLL) circuit is mounted in a semiconductor integrated circuit device to synchronize the output signals of an oscillator serving as reference signals and the operating clocks of a logic circuit for processing data. Further, in recent years, along with the increase in the operation speed of semiconductor integrated circuit devices, in order to speed up the operating clock of a logic circuit, an edge combiner type DLL which can output a multiplied clock of an input signal frequency described in “A 900-MHz Local Oscillator using a DLL-based Frequency Multiplier Technique for PCS Application” by George Chien et al., ISSCC, 2000, p. 105 (Non Patent Document 1) has been used for the delay locked loop (DLL) circuit.
It is known that countermeasures are taken in a delay locked loop so that this DLL circuit satisfies specified operations. For example, DLL malfunction avoiding technologies are disclosed in Japanese Patent Application Laid-Open Publication No. 2005-311543 (Patent Document 1), Japanese Patent Application Laid-Open Publication No. 2005-251370 (Patent Document 2), Japanese Patent Application Laid-Open Publication No. 2001-056723 (Patent Document 3), and Japanese Patent Application Laid-Open Publication No. 2002-64371 (Patent Document 4).
Patent Document 1 discloses a technology in which a control circuit is disposed between a reference clock and an input of a phase comparator and one clock of the reference clock is masked by the control circuit (for example, see FIG. 2 and others in Patent Document 1).
Patent Document 2 discloses a technology in which a comparator enable signal generator is disposed between a reference clock and an input of a phase comparator and the input of the reference clock is controlled by the comparator enable signal generator (for example, see FIG. 3 and others in Patent Document 2).
Patent Document 3 discloses a technology in which a dummy buffer is disposed between a feedback signal and an input of a phase comparator to adjust the difference in delay time from the reference clock input (for example, see FIG. 63 and others in Patent Document 3).